1. Field of the Invention
The present invention relates to an output circuit, such as a level shifter for converting an input signal to a signal of a different level.
2. Description of the Related Art
An example of prior-art output circuit for converting an input signal to a signal of a different voltage level is shown in Japanese Patent Kokai Publication No. H07-226669.
FIG. 15 shows a conventional output circuit shown in FIG. 1 of the above-mentioned publication.
The output circuit shown in FIG. 15 is a level shifter for converting an input voltage to a different voltage level, and includes a Wilson current mirror circuit 10 connected between a power supply potential VDDH node, and nodes N12 and N14. The current mirror circuit 10 is formed of four P-channel MOS transistors (hereinafter denoted by “PMOS's”) 11, 12, 13 and 14. The source of the PMOS 11 is connected to a power supply potential VDDH (e.g., 15V) node, and the drain of the PMOS 11 is connected to a node N11, which in turn is connected to the source of the PMOS 12, and the drain and the gate of the PMOS 12 are connected to a node N12.
The source of the PMOS 13 is connected to the power supply potential VDDH node, and the drain and the gate of the PMOS 13 are connected to the gate of the PMOS 11, and a node N13, which in turn is connected to the source of the PMOS 14. The drain of the PMOS 14 is connected to a node N14.
In the Wilson current mirror circuit 10, the current ratio between the path comprising the PMOS's 11 and 12, and the path comprising PMOS's 13 and 14 is determined based on the β ratios (β=W/L, where W represents the gate width of the MOS transistor, and L represents the gate length of the MOS transistor).
Connected to the node N12 is the drain of an N-channel MOS transistor (hereinafter denoted by “NMOS”) 15 for inducing a current in the current mirror circuit 10. The gate of the NMOS 15 is connected to an inverted input terminal XIN for input of an inverted input voltage Vxin. The source of the NMOS 15 is connected to a ground potential VSS node.
Connected to the node N14 is the drain of an NMOS 16, and the gate of the NMOS 16 is connected to a non-inverted input terminal IN for input of a non-inverted input voltage Vin. The source of the NMOS 16 is connected to the ground potential VSS node.
Connected to the node N14 and the inverted input terminal XIN is an output stage 20, which is formed of a PMOS 21 and an NMOS 22. The source of the PMOS 21 is connected to the power supply potential VDDH node, and the gate of the PMOS 21 is connected to the node N14, and the drain of the PMOS 21 is connected to an output node N21. The output node N21 is connected to the output terminal OUT for an output voltage Vout, and the drain of the NMOS 22. The gate of the NMOS 22 is connected to the inverted input terminal XIN, and the source of the NMOS 22 is connected to the ground potential VSS node.
The operation of the circuit is as follows.
For instance, when the non-inverted input voltage Vin is raised from a low potential level (hereinafter denoted by “L”) to a high potential level (hereinafter denoted by “H”) of a power supply potential VCC (e.g., 5V), and the inverted input voltage Vxin, which is complementary to the non-inverted input voltage Vin, is lowered from “H” to “L,” the NMOS 16 is turned ON (conductive), while the NMOS's 15 and 22 are turned OFF (non-conductive). When the NMOS 16 is turned ON, the node N14 is lowered to “L” of the ground potential VSS, and the PMOS 21 is turned ON. The node N21 is raised to “H” of the power supply potential VDDH (=15V). Thus, the 5V input voltage Vin is converted to 15V power supply potential VDDH. The output voltage Vout is output via the output terminal OUT.
When the NMOS 15 is turned OFF, the current mirror circuit 10 is turned OFF, and the power supply from the power supply potential VDDH to the node N14 is interrupted. As a result, the lowering of the potential at the node N14 is accelerated, and the output terminal OUT is securely maintained at the power supply potential VDDH level.
When the non-inverted input voltage Vin is lowered from “H” to “L” and the inverted input voltage Vxin is raised from “L” to “H,” the NMOS 16 is switched from ON to OFF, while the NMOS's 15 and 22 are switched from OFF to ON. When the NMOS 22 is turned ON, the output node N21 is pulled down to “L” of the ground potential VSS, and the 0V input voltage Vin is output as the output voltage Vout. When the NMOS 15 is turned ON, the current mirror circuit 10 is turned ON, the current flows through the PMOS's 11 to 14, and the potential at the node N14 is pulled up toward the power supply potential VDDH, and is supplied to the gate of the PMOS 21. The PMOS 21 is thereby kept securely in the OFF state, and the power supply from the power supply potential VDDH to the output node N21 is interrupted, and the lowering of the potential at the output node N21 is accelerated, and the output voltage Vout is kept securely at “L” of the ground potential VSS.
When the potential of the node N14 is raised to the vicinity of the power supply potential VDDH level, the potential at the node N13 also rises to the vicinity of the power supply potential VDDH level, and the gate-source voltage Vgs of the PMOS 13 is reduced, and the PMOS 13 is turned into the cut-off state. As a result, the current through the PMOS's 11 and 12 ceases to flow. Thus, the current flowing through the current mirror circuit 10 is only a transient current, and no DC current flows.
As has been described, the output circuit shown in FIG. 15 includes the current mirror circuit 10 that is connected between the node N14 and the power supply potential VDDH node, and the current mirror circuit 10 is controlled by the NMOS 15 which is turned ON and OFF by the inverted input voltage Vxin, so that the operation speed is high, and problems due to the load capacitance associated with the output terminal OUT (the problems that the switching speed, the consumption current, and other characteristics vary depending on the load capacitance associated with the output terminal OUT) can be avoided. Moreover, the operation speed is high, and the time taken for the switching is short, so that the through current flowing from the power supply potential VDDH to the ground potential VSS, which occurs when the PMOS 21 and the NMOS 22 are simultaneously ON is small, and the consumption current is small.
FIG. 16 shows another conventional output circuit shown in FIG. 3 in the above-mentioned publication.
In the output circuit shown in FIG. 16, a PMOS 17 is connected in parallel with the series connection of PMOS's 13 and 14 forming the current mirror circuit 10 identical to that shown in FIG. 15, and the output voltage Vout is fed back to the gate of the PMOS 17, so that when the output voltage Vout is at the ground potential VSS level, the node N14 fully swings to the power supply potential VDDH level. In the output circuit of FIG. 15, when the potential Vn14 at the node N14 is controlled to hold the power supply potential VDDH level, it does not actually reach VDDH, but assumes a value satisfying:VDDH−Vtp≦Vn14≦VDDH, 
(where Vtp is the threshold voltage of the PMOS),
so that the potential Vn14 does not fully swing. In contrast, by the addition of the PMOS 17 in FIG. 16, the potential Vn14 at the node N14 can be made to fully swing to the power supply potential VDDH level, and more secure operation can be realized.
In the conventional output circuits of FIGS. 15 and 16, when the inverted input voltage Vxin rises from “L” to “H,” the NMOS 15 is turned ON, and the current mirror circuit 10 is turned ON, and the current flows through the PMOS's 11-14, and the potential at the node N14 is pulled up toward the power supply potential VDDH, and is supplied to the gate of the PMOS 21.
The node N14 is supplied with the power supply current through the PMOS's 13 and 14, and is pulled up toward the power supply potential VDDH, but this pulling-up is slow. Moreover, because of the delay in the pulling-up, the transition of the PMOS 21 to the OFF state is delayed, and the consumption current flowing through the PMOS 21 is large, and as a result, the consumption current of the output circuit as a whole is large.